DBKWR20

@inproceedings{DBKWR20,
author    = {Dureja, Rohit and Baumgartner, Jason and Kanzelman, Robert and Williams, Mark and Rozier, Kristin Y.},
title     = {{Accelerating Parallel Verification via Complementary Property Partitioning and Strategy Exploration}},
booktitle = {Proceedings of Formal Methods in Computer-Aided Design (FMCAD)},
publisher = {{IEEE/ACM}},
address   = {Haifa, Israel},
editors   = {Ofer Strichman and Alexander Ivrii},
month     = {September},
year      = {2020},
url       = {https://ieeexplore.ieee.org/document/9283641},
abstract  = {This work improves parallel hardware verification for designs with many properties by combining affinity-based partitioning, better work distribution, and less redundant computation. The result is faster verification with lower overall CPU cost across challenging experiments.},
preprint  = {../papers/DBKWR20.pdf},
website   = {http://temporallogic.org/research/FMCAD20/}
}